An integrated circuit comprises a large number of semiconductor devices, such as transistors, that are fabricated on a semiconductor substrate. Integrated circuits are produced in quantity on fabrication lines. Before an integrated circuit is sold, the manufacturer tests the circuit for defects so that corrective action can be taken, if possible. To test the integrated circuit, the manufacturer applies test signals to selected pins of the integrated circuit. To speed up the process of testing large integrated circuits such as memory devices, the signals used to test the integrated circuit differ from the signals used in normal operation, even though the signals in both modes use the same pins of the integrated circuit. Therefore, designers have developed various techniques to differentiate test and normal modes of operation. Because this test mode should not be used once the chip successfully completes the tests, precautions must be taken to assure that the ultimate user of the circuit cannot inadvertently activate the test mode.
In a typical dynamic random access memory (DRAM) device, an out-of-specification voltage, typically 12 volts, is applied to one of the address pins to place the device into test mode for the manufacturer. Once in test mode, the manufacturer can test the operation of the memory device. By using an out-of-specification voltage to enter test mode, it is unlikely that an end user will place the device in test mode inadvertently. As the size of integrated circuits gets smaller, this technique becomes less reliable and the risk of damaging the circuit by shorting out components increases by exceeding the capacity of the circuit to pass current associated with the higher voltage.
In other memory devices, the test circuitry uses a latch circuit to determine when to enter test mode. These devices suffer from the problem that the ultimate user of the device could inadvertently initiate the test mode when turning on a computer that uses the device. Because it is not possible to disable the latch from entering the test state, the latch could be in the test state at power up thus allowing the ultimate user to activate the test circuitry.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a circuit and method for entering test mode that reduces the risk of damage to the device and reduces the chances that the ultimate user will inadvertently enter test mode.